1. Field of the Invention
The present invention generally relates to data processing techniques and, in particular, to a system and method for synchronizing video data streams.
2. Related Art
Some graphical display systems employ a plurality of graphics pipelines, sometimes referred to as “graphics accelerators” or “graphics adapters,” to render graphical data in parallel. Each of the graphics pipelines outputs a video data stream that is utilized by one or more display devices to display a graphical image based on the graphical data rendered by the graphics pipelines.
In many situations, the video data streams output by the graphics pipelines within a graphical display system are asynchronous. As known in the art of video signaling, the term “asynchronous video data streams” refers to a set of video data streams that are not frame synchronized with respect to one another. The timing of “asynchronous video data streams” is often controlled by clock signals derived from different clocks, sometimes referred to as “crystals.” The term “synchronous video data streams,” on the other hand, refers to a set of video data streams that are frame synchronized with respect to one another. The timing of “synchronous video data streams” is normally controlled by the same clock signal or at least clock signals derived from the same clock.
For a variety of reasons, it may be desirable to synchronize a set of asynchronous video data streams or, in other words, to convert a set of asynchronous video data streams into a set of synchronous video data steams. Synchronization of asynchronous video data streams is usually achieved via a triple buffer configuration. In this regard, buffering logic writes graphical data from an incoming video data stream into a first frame buffer within the triple buffer configuration. While the graphical data is being written into the first frame buffer, a display device receives a frame of graphical data from a second frame buffer of the triple buffer configuration. A third frame buffer in the triple buffer configuration stores graphical data defining the next image frame that is to be displayed by the display device.
After the display device completely receives the frame of graphical data stored in the second frame buffer, a buffer swap eventually occurs. In response to a buffer swap, the display device begins to receive data from the frame buffer (i.e., the third frame buffer) storing the graphical data of the next image frame, and the buffering logic begins writing the incoming video data stream to the frame buffer (i.e., the second buffer) that was read by the display device prior to the buffer swap. Moreover, the remaining frame buffer (i.e., the first frame buffer), which was being written to prior to the buffer swap, now stores graphical data that will be later used to display an image frame in response to the next buffer swap.
Moreover, each of the video data streams from the graphics pipelines in a graphical display system may be fed into the triple buffer configuration described above. By synchronizing the buffer swaps in each of the triple buffer configurations, each of the video data streams can be synchronized with respect to each other. Thus, the triple buffering techniques described above are suitable for synchronizing the video data streams output from the graphics pipelines of a graphical display system.
However, the aforedescribed synchronization techniques require at least three buffers for synchronizing a video data stream. Not all graphics cards include three or more buffers making such graphics cards unsuitable for synchronizing video data streams according to the aforedescribed techniques.